The present invention relates generally to optical data transmission, and, more particularly, to timing alignment among modulated signals in optical transmission systems.
In optical transmission with data formats other than simple NRZ format, such as a returned to zero (RZ) format, a periodically modulated light source that generates a clocklike pulse stream instead of a continuous wave light source is often used.
To achieve stable and optimized operation, the optical data modulation needs to have a fixed time delay relative to the modulated light source. For example, optimal performance of RZ transmission is usually achieved when the peak of the modulated light overlaps with the center of the data bit slot.
A conventional method to make this timing alignment is to shift the timing of the modulated light. This is because it is much easier to make time delay on a clock signal than on a broadband data signal. The timing shift of clock is made available by placing a voltage-controlled phase shifter before or after the clock driver, which is used to drive a clock modulator or a direct modulated laser (DML). The phase shift is thus at the line rate frequency. For example, if the data rate is 10 Gbps, the phase shift is at 10 GHz. In some other conventional RZ pulse generation schemes, half rate frequency can also be used for over-driving a Mach-Zehnder (MZ) modulator to generate line rate clock pulse trains. In this case, the phase shift is at a half rate frequency. In order to prevent the slow drift over time from the optimal point caused by mechanical variation, thermal variation, or other environmental changes in the relative phase, a feedback loop is often implemented to lock the relative timing between the data modulation and the light source.
In more complex modulation formats for high capacity optical transmission, there are more than one driving data signals, such as double data modulation has two driving data signals. Relative timings between the multiple driving signals are adjusted in a similar fashion, with the exception that variable delay lines are implemented rather than phase shifters, since the latter generally narrows frequency pass band and would distort the signals.
However, the high frequency phase shifters used in this conventional method are inherently complex and expensive, especially if the phase shift needs to cover a minimum 360 degrees, also known as one bit slot to those skilled in the art. For example, the insertion loss of the phase shifter may vary a lot over the phase shift range. It is also difficult to make phase shifters that have linear phase shift versus control voltage over the large range.
Variable delay lines with broad frequency responses used in double data modulation are even more expensive and difficult to use. Furthermore, when a feedback loop is used to lock the relative timing, the dithering phase shift may add undesirable time jitters to the output optical data signals.
Therefore, it is desirable to devise improved method and system for shifting and locking the timing among the driving signals in the above applications.